1. Field of the Invention
The present invention relates to an arrangement and method of accessing a multiple-plane (viz., multiple-bit) frame buffer in a computer system using a raster-scan type display, and more specifically to such an arrangement and method which is capable of effectively reducing the number of accesses to the frame buffer.
2. Description of the Prior Art
Computer graphics has a rapidly growing importance in the computer field. It is known in the art that there are two types of displays for use in computer graphics: one is a video display (viz., raster-scan type display) while the other is a matrix-addressed storage device such as a plasma plane.
The instant invention is concerned with improvements in a video signal generator which is arranged to supply a raster-scan type display (viz., CRT display) with three analog signals each indicating the intensity of one of the three primaries (red, green and blue).
Before turning to the present invention it is deemed advantageous to briefly discuss prior art with reference to FIGS. 1 and 2.
FIG. 1 is a schematic illustration of a known video signal generator 10 which is operatively provided between a CRT display 14 and a frame buffer controller 12 coupled to a computer system bus. The video signal generator 10 includes a video controller 16 and a multiple-plane frame buffer 18.
The video controller 16 is comprised of a color look-up table 20, a pixel register 22, digital-to-analog (D/A) converters 24a-24c, and a display scan sync signal generator 26 which produces horizontal and vertical sync signals. The multiple-plane (viz., multiple-bit) frame buffer 18 takes the form of a 4-bit-per-pixel frame buffer in this particular case and accordingly includes four memory planes depicted by I (Intensity per pixel), R (Red), G (Green) and B (Blue).
The binary data stored in the frame buffer 18 are utilized as addresses to a table of colors which are prestored in the look-up table 20 and which are defined by red, green and blue components. Consequently, the 4-bit-per-pixel frame buffer 18 is able to index 16 colors from 4096 colors (for example) previously stored in the look-up table 20. The bit stream from the color look-up table 20 is applied to the pixel register 22 whose contents (12-bit for example) are applied to the CRT display 14 after being converted into corresponding analog signals (denoted by R', G' and B') by the D/A converters 24a-24c.
The above mentioned video signal generator 10 is well known to those skilled in the art and hence further description thereof would be redundant and therefore omitted for the sake of brevity. It goes without saying that the frame buffer 18 is not limited to the above mentioned 4-bit-per-pixel type.
A known technique for accessing the frame buffer 18 will be discussed with reference to FIG. 2 which is a sketch given for a better understanding of the drawback encountered with the prior art.
FIG. 2(a) illustrates an 8.times.8 bit matrix wherein a character "A" is indicated in a white color on a red color background. The frame buffer controller 12 accesses the frame buffer 18 for writing thereto pixel data representative of the character "A".
According to the prior art, the frame buffer controller 12 is required to access the frame buffer 18 twice in this particular case: the first access is for writing the image (viz., character) color (white) pixel data as shown in FIG. 2(b) while the second is for writing the background color (red) pixel data as shown in FIG. 2(c). Especially, in the case where the background is unicolored over an entire display frame, it is time consuming to access the frame buffer for writing the background pixel data thereto.